1. Write synthesizable VHDL code that will generate the given waveform (W). Use a single process. Assume that a clock with a 1 s period is available as an input.
2. A BCD adder adds two BCD numbers (each of range 0 to 9) and produces the sum in BCD form. For example, if it adds 9 (1001) and 8 (1000) the result would be 17 (1 0111). Implement such a BCD adder using a 4-bit binary adder and appropriate control circuitry. Assume that the two BCD numbers are already loaded into two 4-bit registers (A and B), and there is a 5-bit sum register (S) available. You need some kind of correction to get the sum in the BCD form, because the binary adder produces results in the range 0000 to 1111 (plus a carry in some cases). If any addition is required for this correction, use the same adder (i.e., you can use only one adder). Use multiplexers at the adder inputs to steer the appropriate numbers to the adder in each cycle. Assume a start signal to initiate the addition and a done signal to indicate completion.
(a) Draw a block diagram of the system. Label each component appropriately to indicate its functionality and size.
(b) Describe step-by-step the algorithm that you would use to perform the addition. Explain and illustrate the correction step.
(c) Draw a state graph for the controller.