a.) Write a VHDL module for a 4-bit adder, with a carry-in and carry-out, using an overloaded addition operator and std_logic_vector inputs and outputs.
b.) Design an 8-bit subtractor with a borrow-out, using two of the 4-bit adders you designed in (a), along with any necessary gates or inverters. Write a VHDL module for the subtractor.
c.) Simulate your code and test it using the following inputs: 11011011 - 01110110, 01110110 - 11011011