a) Write a Verilog model of the 4-bit 2-to-1 Multiplexer with the Enable input; if Enable==1, then a selected input is connected to the output, otherwise the Multiplexer is in the high-impedance state;
b) Write a Verilog testbench for the multiplexer and expected Simulation Report.
2. Write a Verilog model for the Logic Unit (LU) that performs the following bitwise logic operations: AND, OR, XOR, NAND, NOR, XNOR.
LU (operand1, operand2, opcode, result). The operands and result are 8-bit numbers.
3. Write a Verilog behavioral description of the following circuit:
F(A,B,C,D) = Sm(1,12,15)