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Write a simulator for a 1-way direct mapped cache make the

1. Normally, dependences cause trouble with pipelined CPUs. Are there any optimizations that can be done with WAW dependences that might actually improve matters? What?

2. Rewrite the Mic-1 interpreter but having LV now point to the first local variable instead of to the link pointer.

3. Write a simulator for a 1-way direct mapped cache. Make the number of entries and the line size parameters of the simulation. Experiment with it and report on your findings.

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Computer Engineering: Write a simulator for a 1-way direct mapped cache make the

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