Write a DFF model with asynchronous clear, asynchronous set, synchronous clear and synchronous set. Asynchronous controls have priority over synchronous controls. In addition, synchronous clear has higher priority over synchronous set. asynchronous set has priority over asynchronous clear.
Make sure to use only Verilog behavior constructs to model your DFF.
what to turn in:
Your Verilog behavioral models for the DFF.
Verilog Test fixture with sufficient number of vectors to show that your DFF works as expected
The simulation outputs for the test fixture.