(a) Write a behavioral VHDL description of the state machine you designed in Problem 1.13. Assume that state changes occur on the falling edge of the clock pulse. Instead of using if-then-else statements, represent the state table and output table by arrays. Compile and simulate your code using the following test sequence:
X should change 1/4 clock period after the rising edge of the clock.
(b) Write a data flow VHDL description using the next state and output equations to describe the state machine. Indicate on your simulation output at which times S and V are to be read.
(c) Write a structural model of the state machine in VHDL that contains the interconnection of the gates and D flip-flops.
Problem 1.13
A sequential circuit has one input (X) and two outputs (S and V). X represents a 4-bit binary number N, which is input least significant bit first. S represents a 4-bit binary number equal to N + 2, which is output least significant bit first. At the time the fourth input occurs, V = 1 if N + 2 is too large to be represented by 4 bits; otherwise, V = 0. The value of S should be the proper value, not a don't care, in both cases. The circuit always resets after the fourth bit of X is received.
(a) Derive a Mealy state graph and table with a minimum number of states (six states).
(b) Try to choose a good state assignment. Realize the circuit using D flip-flops and NAND gates. Repeat using NOR gates. (Work this part by hand.)
(c) Check your answer to (b) using the LogicAid program.Also use the program to find the NAND solution for two other state assignments.