1. Write a behavioral VHDL program for the above 4-bit carry-select adder, and work through the same synthesis process.
2. Design an 8-bit ALU by first composing a hierarchical VHDL program, compile and simulate the design, and then synthesize the logic circuit.The report should include: the VHDL program, the captured logic circuit schematic diagram, the simulation waveform chart, the synthesis process report, and the FPGA CLB usage map; all produced by using Xilinx WebPACK ISE design software.