Write a behavioral VHDL code module for a 6-bit up-down counter. If U = 1, and D = 0, the counter will count up, and if U=0, and D=1, the counter will count down. If U = D = 0, or U = D = 1, the counter will hold its state. The counter should also have an asynchronous active-low preset signal PreN that sets all flip-flips to 1. Please type or write neatly.
Test and provide code for these test cases.
- preset - set U = 0 0 0 1 1 1 - set D = 1 1 1 0 0 0