The overall goal is to design a dual port memory between two microcontrollers, as described in Section 10.3.2. There are a few ways to handle simultaneous requests that do not require dynamic bus cycle stretching with a MRDY signal. The first possibility is to design a hardware semaphore that the two microcontrollers can use to request access to the memory. In this scheme, only one microcontroller can access the memory at a time. A second approach is to give priority to the master computer, and if there is a conflict, let the master have access and ignore the slave. In this scheme, you'll have to add software checking to the slave to verify that a read/write access occurred. The third scheme requires design of both microcontrollers. The microcontrollers can be designed to run off external clocks. In this scheme, you generate a bus clock separately and feed both microcontrollers with the same clock, but out of phase. Then you design the memory interface to occur in the second half of the cycle (when E = 1). In this way, the bus conflict is avoided. The second part of the lab is the design of low-level device driver software to implement bidirectional communication. Run main programs in each microcontroller that determine the maximum bandwidth of this channel. Will it be faster than a simple SPI channel?