RDRF interrupts are armed so that interrupts occur when new data arrives into the 9S12. Consider the situation in which a FIFO queue is used to buffer data between the RDRF ISR and the main program. The SCIhandler reads SCIDRL and saves the data by calling Fifo_Put. When the main program wants input it calls SCI_InChar, which in turn calls Fifo_Get. Experimental observations show this FIFO is usually empty, and has at most three elements. What does it mean?
a) The system is CPU bound
b) Bandwidth could be increased by increasing FIFO size
c) The system is I/O bound
d) The FIFO could be replaced by a global variable
e) The latency is small and bounded
f) Interrupts are not needed in this system