Problem
A cache memory may be operated in either a serial or a parallel mode, In the serial access mode, the cache is examined for data, and if a miss occurs the main store is accessed. In the parallel access mode, both the cache and the main store are accessed simultaneously. If a hit occurs, the access to the main store is aborted. Assume that the system has a hit-ratio h and that the ratio of cache memory access time to main store access time is k < 1). derive expressions for the speedup ratio of both a parallel access cache and a serial access cache. if a serial mode cache is to be used, and a 10 percent penalty in speedup ratio over the corresponding parallel access cache can be tolerated, what must the value of h be to achieve this? assume that the main store access time is 150 ns and that the cache access time is 30?
The response should include a reference list. Double-space, using Times New Roman 12 pnt font, one-inch margins, and APA style of writing and citations.