Response to the following:
Design the circuit in Fig. to obtain a. dc voltage of +0.1 V at each of the drains of Q1:and Q2:when vG1 = vG2 = 0 V. Operate all transistors at VOV = 0.15 V and assume that for the process technology in which the circuit is fabricated, Vtn = 0.4 V and μnCox = 400 μA/V2. Neglect channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1:Q2:Q3:and Q4: What is the input common-mode voltage range for your design?
