Task 1
Suppose the hypothetical machine in Figure 1.3 and Figure 1.4 of the text book (see below) is modified, where the memory
address is now 8 bits instead of 12. Therefore, the instruction format subsequently becomes:
0001 0000 xxxx xxxx (or 10XX in Hexadecimal) = Load AC from memory location XX.
0010 0000 xxxx xxxx (or 20XX in Hexadecimal) = Store AC to memory location XX.
0101 0000 xxxx xxxx (05 50XX in Hexadecimal) = Add to AC from memory XX.
Also, the following new instructions are added:
0110 xxxx xxxx xxxx (or 6XXX in Hexadecimal) = Load Branch Control (BC) register with the value of XXX.
0111 0000 0000 0000 (or 7000 in Hexadecimal) = Increment BC by 1.
1000 xxxx yyyy yyyy (or 8XYY in Hexadecimal) = Jump to instruction at memory location YY (the Program counter (PC) value
changes to YY) if BC is not equal to X, otherwise, the CPU executes the next instruction (the PC value increments by 1).
Design a set of instructions you would use to add the value stored in memory location "20" by the value stored at memory
location "29" ten (15) times. That is, if is the value at location 20, and is the value location 29 then you are being asked to
compute the value of
In your program, you must show the changes of all relevant memory and register values for at least two cycles or loops. You
may assume the PC before executing the program has the value of "F0". You also need to give a word description for each
instruction you design.
Explain the occurrence of locality of reference in this scenario.
Task 2
Describe a Cache System. Can you think of any real-life scenario (except the library-bookshelf scenario) where you can draw an
analogy to a cache system?
Consider a memory system with the following parameters:
100 ns
0.01 cents/bit
ns
cents/bit
What is the cost of 1 MByte of main memory?
What is the cost of 1 MByte of main memory using cache memory technology?
If the effective access time is 10% greater than the cache access time, what is the hit ratio H?
Task 3
Assume that at time 5 no system resources are being used except for the processor and memory. Now consider the following
events:
At time 5: P1 executes a command to read from disk unit 3.
At time 15: P5's time slice expires.
At time 18: P7 executes a command to write to disk unit 3.
At time 20: P3 executes a command to read from disk unit 2.
At time 24: P5 executes a command to write to disk unit 3.
At time 28: P5 is swapped out.
At time 33: An interrupt occurs from disk unit 2: P3's read is complete.
At time 36: An interrupt occurs from disk unit 3: P1's read is complete.
At time 38: P8 terminates.
At time 40: An interrupt occurs from disk unit 3: P5's write is complete.
At time 44: P5 is swapped back in.
At time 48: An interrupt occurs from disk unit 3: P7's write is complete.
For each time 22, 37, and 47, identify which state each process is in.
If a process is blocked, further identify the event on which is it blocked.