Problem
We examine how pipelining affects the clock cycle time of the processor. Let us assume that individual stages of the datapath have the following latencies:
IF: 250ps
ID: 350ps
EX: 150ps
MEM: 300ps
WB: 200ps
Also, assume that instructions executed by the processor are broken down as follows:
alu: 45%
beq: 20%
lw: 20%
sw: 15%
1. What is the clock cycle time in a pipelined and non-pipelined processor?
2. What is the total latency of an LW instruction in a pipelined and non-pipelined processor?
3. If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?