Problem
Consider a workload that is
20% branches (80% of which are taken),
20% loads,
10% stores,
50% ALU instructions.
Assume that no load is immediately followed by a use.
Assume the following cycle counts for each instruction type:
Branches: 3-cycles
Load Instructions: 5
Store Instructions: 4
ALU-Instructions: 4 cycles
1. What is the CPI of a multi-cycle processor executing workload W?
2. What is the CPI of a 5-stage (FDXMW) pipelined processor with no branch predictor executing Workload W?
3. What is the CPI of a 5-stage (FDXMW) pipelined processor with a branch predictor with 90% accuracy executing Workload W?