In computer processors, the data path often consists of the following functional blocks. The instruction register stores the current instruction to be executed. The program counter (PC) stores the address of the next instruction to be fetched. The memory address register (MAR) is a register that either stores the memory address from which data will be fetched to the CPU or the address to which data will be sent and stored.
The memory data register (MDR) is a register of a computer's control unit that contains the data to be stored in the computer storage (e. g. RAM), or the data after a fetch from the computer storage.
1. What are the advantages and disadvantage of fixed size instructions and varying size instructions? How does the datapath hardware deal with both?
The pipeline itself comprises a whole task that has been broken out into smaller sub-tasks. The concept actually has its roots in mass production manufacturing plants, such as are seen in the auto industry where one station is responsible for putting in the engine, another the tires, another the seats, and so on.
In computers, the same basic logic applies, but rather than producing something physical on an assembly line, it is the workload itself that gets broken down into smaller stages.
2. Processor pipelining does not help the instruction latency, it only helps the total program throughput. Do you agree or disagree? Provide real-life examples to support your position.