We have multiple instances in RTL (Register Transfer Language), do you do anything special during synthesis stage?
Whereas writing RTL(Register Transfer language),say in Verilog or in VHDL language, we don't write the similar module functionality again and again, we use a method name as instantiation, where in as per the language, the instantiation of a module will behave like the parent module in terms of functionality, where during synthesis stage we require the full code so that the synthesis tool can study the logic , structure and map it to the library cells, so we use a command in synthesis , known as "UNIQUIFY" which will replace the instantiations with the real logic, because once we are in a synthesis stages we have to visualize as real cells and no more modelling just for functionality alone, we need to visualize in-terms of physical world as well.