Question 1) Write down VHDL code for binary to 7 segment display.
Question 2) Write about the concept of overloading with the help of suitable example.
Question 3) Write a counter model with the clock input clk of type bit, and an output q of type integer. Behavioral architecture body must contain a process which declares a count variable initialized to zero. Process must wait for changes on clk. When clk changes to ‘1’ the process must increment the count and assign its value to the output port.
Question 4) Make the “clk1” and “clk2” waveforms for following two process statements. Both “clk1” and “clk2” are signals for the type bit.
P1: Process is Begin
Clk1 <=”1” after 5 ns, “0” after 10 ns;
Wait for 10ns;
End;
P2: Process is
Clk2<=’1’ after 5 ns;
Clk2<=’0’ after 10 ns;
Wait for 10ns;
End;
Question 5) Design a behavioural model of a RAM with generic constants governing the read access time, minimum write time, the address port and the data port width.
Question 6) Explain the 8-bit serial to parallel and parallel to serial shift register and write code for the same.
Question 7) Write brief notes on:
(a) Guarded signals with the help of examples.
(b) FPGA Vs. CPLD designing.