1. Using only D FFs, and 1-of-4 MUXs, design a 3-bit register that can hold the present data, shift right, shift left, and load new data in parallel.
2. Design a four-bit circulate-right-shift register using (a) D FFs and (b)JK FFs.
3. Verify the Boolean equations of the four-bit down counter introduced in Section 9.2.