Open-drain CMOS logic is used to allow several gates to drive a common bus. Each gate output can be in a ‘Z' state or in a ‘0' state. Only one gate at a time should assert a ‘0' state. The bus is in a ‘1' state if all the gates driving it are in a ‘Z' state. This is achieved by a pull-up resistor. Design a four-value logic type to model this bus and a suitable resolution function. (The pull-up resistor does not need to be explicitly modelled.) Write a model of an open-drain two-input NAND gate, and hence model a bus driven by four such gates. To simulate this model, the type definitions and the resolution function will need to be put into a package. You may wish to return to this problem after packages have been described in Chapter 7.