(Actel Logic Module) Re-implement the FSM of Exercise 9.4 using Actel R-cells and C-cells.
Exercise 9.4
(Counter-based FSMs) Construct a finite-state machine with nine states and two inputs in addition to reset. On reset, the machine starts in the middle state of the nine. When the left input is asserted, it transitions one state to the left; when the right input is asserted, it transitions one state to the right. If it reaches a state at either end of the chain, it stays in that state until the next reset. The leftmost state will assert the Left-LED output, the rightmost state will assert the Right-LED output. Use the up/down counter of Figure 9.5 to implement this state machine with as little external logic as possible. (Hint: Consider using the load signal to implement the reset behavior.)
