Question: The diagram below is an arbitration circuit taken from Motorola application note DC003, Using the MC68020 as a dedicated DMA controller. The circuit has an EXT_REQ* (external arbitration request) input that is asserted active-low by a device that wishes to request the system bus. When the arbitration process has been completed, the circuit asserts its GO_EXT* output to indicate that the bus requester now has control of the bus. Signals BG*, BGACK*, and BR* are connected to the 68000 bus arbitration interface, and AS*, UDS*/LDS*, DTACK*, and BERR* are the 68000's asynchronous bus control signals. The two inverters marked OtC (open collector) can actively pull their outputs down to a low level, but they cannot put their outputs high. When the outputs of these open-collector circuits are high, they are passively pulled up to Vcc by the resistor
By means of a timing diagram, analyze the operation of this circuit (assume that the requester asserts EXT_REQ* to begin the arbitration sequence)
