Consider a 32 bit number consists of two parts: a 24 bit whole part and an 8 bit fractional part For instance the number:
0000 0000 0000 0000 0000 0111 0110 0000
Represents:
7.375
In this lab you will design a convergent rounder that is different in functionality from the regular rounder that you are familiar with.
The convergent rounder in this lab rounds the number based on fractional part of the number. The following is the criteria that you need to consider when designing this rounder:
1. When the fractional part is larger than 0.5, the number is rounded up.
2. When the fractional part is less than 0.5 the number is rounded up.
3. When the fractional part is 0.5, the number is rounded up if the whole part is odd and rounded down is the whole part is even.
Design a synthesizable convergent rounder with the above specification. Design your circuit for minimum area. Your design should work with both signed and unsigned numbers.
1. Draw a block diagram of the complete design that implements your algorithm.
2. Write a VHDL code to model this division by constant circuit
3. Write a VHDL testbench to verify your design. Present a test vector that verifies the functionality of the design for all critical cases. Your testbench should cover both signed and unsigned numbers.