The capacitance cl is found to be 15 f f consider the

Question

In this and the following problem, we investigate the dynamic operation of a two-input NAND gate realized in the dynamic logic form and fabricated in a CMOS processtechnology for which k¹ n = 4k¹ p = 500 μA/V2, Vtn = -Vtp = 0.4 V, and VDD = 1.2 V. To keep CL small, minimum-size NMOS devices are used for which W/L = 1.5 (this includes Qe). The PMOS precharge transistor Qp has W/L = 3. The capacitance CL is found to be 15 f F. Consider the recharge operation with the gate of Qp at 0 V, and assume that at t =0, CL is fully discharged. Calculate the rise time of the Output voltage, defined as the time for vY to rise from 10% to 90% of the final value of 1.2 V.