Suppose that two numbers in signed two's complement form have been added. S1 is the sign bit of the first number, S2 is the sign bit of the second number, and ST is the sign bit of the total. Suppose that we want a logic circuit with output E that is high if either over flow or under flow has occurred; otherwise, E is to remain low.
a. Write the truth table.
b. Find an SOP expression composed of min terms for E.
c. Draw a circuit that yields E, using AND, OR, and NOT gates.