1. Design an 8-input AND gate with an electrical effort of six using pseudo-nMOS logic. If the parasitic delay of an n-input pseudo-nMOS NOR gate is (4n + 2)/9, what is the path delay?
2. Simulate a pseudo-nMOS inverter in which the pMOS transistor is half the width of the nMOS transistor. What are the rising, falling, and average logical efforts? What is VOL?