Showing output resistance with vsig set to zero


Problem:

1. An alternative equivalent circuit of an amplifier fed with a signal source (vsig, Rsig) and connected to a load RL is shown in Fig. P7.62. Here Gv o is the open-circuit overall voltage gain,

1751_Open circuit.jpg

and Rout is the output resistance with vsig set to zero. This is different than Ro. Show that

174_Output resistance.jpg

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Electrical Engineering: Showing output resistance with vsig set to zero
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