Segment Registers
The 8086 addresses a segmented memory unlike 8085. The complete 1 megabyte memory, which 8086 is capable to address is divided into 16 logical segments.Thuseach segment has 64 Kbytes of memory. There are 4 segment registers, viz, Data Segment Register (DS), Code Segment Register (CS), and Segment Register (SS). AndExtra Segment Register (ES) Stack The code segment register is utilized for addressing a memory location in the code segment of the memory, where the executable program is stored. As similar, the data segment register points to the data segment of the memory, where the data is resided. The additional segment also refers to a segment which really is another data segment of the memory. Thus the additional segment also contains data. The stack segment register is utilized for addressing stack segment of memory. The stack segment is that type segment of memory which is utilized to store stack data. The CPU utilizes the stack for provisionally storing important data, for example the contents of the CPU register which will be needed at a later stage. The stack grows down, for example. the data is pushed onto the stack in the memory locations with decreasing addresses. When this information will be needed by the CPU, they will be popped off from the stack. When addressing of any location in the memory bank, the physical address is computed from 2 parts, the first is segment address and the second offset. The segment registers contain 16-bit segment base addresses, related to different type of segments. Any of the pointers,BX andindex registers can contain the offset of the location to be addressed. The benefit of this scheme is that in place of maintaining a 20-bit register for a physical address, the processor only maintains two 16-bit registers which are within the word length capacity of the machine. Thus the DS, CS, SS and ES segment registers respectively contain the segment addresses for thedata, code, stack and extra segments of memory. It can be noted that all these segments are the logical segments. They can or cannot be physically separated. In other terms, a single segment may require more than one memory chip or more than 1 segment may be accommodated in a single memory chip.