Design a circuit that takes as input four BCD encoded digits representing a calendar year after 1582 and produces a single output, LY, which is one if the year is a leap year, zero otherwise. Leap years are years which are divisible by four except that years divisible by 100 are not leap years unless they are also divisible by 400.
You should follow the same general guidelines you used for Project 1: you must describe your design approach, create truth tables where appropriate, use K-maps to minimize your equations, and produce a Verilog behavioral dataflow description along with a test bench and outputs to demonstrate your design works. You must also use design hierarchy: that is you should create a DivisibleByFour module which is incorporated into the top-level module.Some hints: Divisibility by 100 is trivial for BCD inputs. Since all multiples of 100 are divisible by 4, you only need to examine the two least significant digits of the year (representing tens and ones) to determine if the year is divisibly by 4.