The block diagram for an elevator controller for a two-floor elevator follows. The inputs FB1 and FB2 are 1 when someone in the elevator presses the first or second floor buttons, respectively. The inputs CALL1 and CALL2 are 1 when someone on the first or second floor presses the elevator call button. The inputs FS1 and FS2 are 1 when the elevator is at the first or second floor landing. The output UP turns on the motor to raise the elevator car. The output DOWN turns on the motor to lower the elevator. If neither UP nor DOWN is 1, then the elevator will not move. R1 and R2 reset the latches (described below); and when DO goes to 1, the elevator door opens. After the door opens and remains open for a reasonable length of time (as determined by the door controller mechanism), the door controller mechanism closes the door and sets DC = 1. Assume that all input signals are properly synchronized with the system clock.
Please apply the following guidelines to your design.
If you were to realize an elevator controller that responded to all of the inputs FB1, FB2, CALL1, CALL2, FS1, FS2, and DC, you would need to implement logic equations with nine or more variables (seven inputs plus at least two state variables). However, if you combine the signals FBi and CALLi into a signal Ni (i = 1 or 2) that indicates that the elevator is needed on the specified floor, you can reduce the number of inputs into the control circuit. In addition, if the signal Ni is stored so that a single pulse on FBi or CALLi will set Ni to 1 until the control circuit clears it, then the control circuit will be simplified further. Using a D flipflop and a minimum number of added gates, design a storage circuit that will have an output 1 when either input (FBi or CALLi) becomes 1 and will stay 1 until reset with a signal Ri.
Using the signals N1 and N2 that indicate that the elevator is needed on the first or second floor (to deliver or pick up passengers or both), derive a state graph for the elevator controller. (Only four states are needed.)
Realize the storage circuits for N1 and N2 as describe in the design specification.