Question 1) Why is the presence of a hardwired zero register so important in RISC architectures?
Question 2) The MIPS ISA does not include a negate instruction. Provide another MIPS assembly instruction that negates the contents of register 3 and writes the result into register 4.
Question 3) How many registers can a register specifier of 7 bits address?
Question 4) Name one key benefit and one key drawback of large register specifiers.
Question 5) Compute the address from which the load byte instruction below reads, the address to which the branch transfers control if taken, and the address that is the target of the jump instruction.
0x80000000: lui $t2, 1
0x80000004: lb $t3, 1($t2)
0x80000008: beq $t3, $zero, 1
0x8000000C: j 1