Post interrupts - computer architecture:
Post interrupts
- Exact interrupts
- examine interrupt bit on entering WB
- Longer latency
Handle immediately
- interrupt may take place in order different from sequential CPU
- not completely precise
- May cause implementation headaches!
Other complications
- odd bits of state (for instance :CC)
- early-writes (for instance auto increment)
- out-of-order execution
- dynamic scheduling
- instruction buffers and prefetch logic