Assignment : Inputs, Outputs, and Logic Gates
In this assignment we will build on the program we created in Module 3.
Before the Lab: Complete Module 3.
Part 1:
In Module 3, we implemented an AND gate. Modify your code to implement an OR gate instead. Upload and test your program on the Basys2. Create the truth table based on your test results. Is it correct?
Modify your code to implement the following gates:
o AND
o NAND
o OR
o NOR
o XOR
o XNOR
Test each gate and write their corresponding truth tables. Use the code snippet below to get you started.
Notice how we can use comments to exclude pieces of code that are not currently in use. When you want to test a given gate, simply comment out the others. This lets you switch between different gates without having to rewrite them every time.
Part 2:
In Part 1 we implemented six different gates and displayed the result of each on an LED. However, commenting and un-commenting each time we want to use a different gate can get tedious, as it requires us to re-compile and re-upload the program each time. the Basys2 board gives us access to eight LEDs. Why not display the outputs of all the gates simultaneously, each on its own LED?
a) Begin by defining new constraints in the implementation constraints file for five additional LEDs. Note that we do not need additional switches, as the same switches will be used as input for all the gates.
b) In your sub-module, declare five additional outputs and assign them to the corresponding gates you implemented in Part 1. Give the outputs descriptive names, such as "and_output", "or_output", etc.
c) Analyze your top module and determine what needs to be changed to account for the additional outputs. See the code below for a hint.
Test your completed program. You should have two switches controlling the inputs, and six LEDs displaying the output, one for each gate. Using the truth tables you wrote in Part 1, verify that each LED displays the correct result for all possible input combinations.What to hand in:
Hand in the truth tables you wrote in Part 1, and the following files you modified in Part 2:
o The implementation constraints file (*.ucf)
o The top module (*.vhd)
o The sub-module (*.vhd)