In the pipelined version of src the branch instructions


Problem

In the pipelined version of SRC, the branch instructions have a branch delay slot to avoid stalling the pipeline for a cycle. Assume that the compiler schedules instructions into the branch-delay slot. In this context, consider the implications of the brl instructions scoring PC = 4 in the link register.

a. What problem does this pose for subroutine return?

b. How should the compiler handle this problem?

 

Request for Solution File

Ask an Expert for Answer!!
Computer Engineering: In the pipelined version of src the branch instructions
Reference No:- TGS02738148

Expected delivery within 24 Hours