Over-registered Counter
In example 7.5, an analysis of the counter designed in example 6.6 was made. Compile the code presented in the latter to confirm the answers presented in the former.
Example 7.5:
Over-registered Counter Consider the counter designed in example 6.6.
a) How many flip-flops are needed to implement it?
b) What happens if line 27 (END IF;) of that code is moved to the position between lines 41 and 42?
Example 6.6:
Slow 0-to-9 Counter with SSD Add an SSD (Seven-Segment Display-described in section 12.1, see figure 12.2) to the output of the 0-to-9 counter designed in example 6.2, such that the state of the counter can be visually inspected. This arrangement is depicted in figure 6.9. Besides the counter and the SSD, an SSD driver is also shown, which is a combinational circuit that converts the 4-bit output from the counter (called count) into a 7-bit signal (called ssd ) to feed the seven segments of the display. Assume that the clock frequency is 50 MHz, which
