FSM with Repetitive States Figure 15.8 shows an FSM with an apparent single loop. Note that state B must be repeated 8 times, then state C must occur, with this sequence (B - C) repeated 7 times before proceeding to state D. A similar procedure must occur in states F - G.
(a) Implement this machine using the pointer-based technique and VHDL or SystemVerilog. Start by making the proper adaptations (using pointer(s)) in the state transition diagram. Create an array of constants to be placed at the output in states B and F, and chose numeric values for y A, y C, y D, etc.
(b) Show simulation results. To ease the inspection of the results, use 3 instead of 8 and 2 instead of 7 in the repetitions.
