1. Develop a logic circuit, using only NAND gates, to implement a circuit to meet the requirements of the truth table shown below.
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
2. Develop a logic circuit, using only NAND gates, to implement a circuit to meet the requirements of the truth table shown below.
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
3. Implement the truth table shown below using the minimum number of NAND gates. Use 2-, 3- , and/or 4-input NAND gates as required to minimize gates.
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1