(Counter/Register Applications) Design a 2-bit binary up-counter to the following specification. The counter has five inputs (not including the clock) and three outputs. The inputs are CLR, LOAD, COUNT, LB, and LA. CLR takes precedence over LOAD, which in turn takes precedence over COUNT. The outputs are B, A, and RCO.
When CLR is asserted, the flip-flops of the counter are reset to 0. If LOAD is asserted (when CLR is not asserted), the flip-flop's contents are replaced by the LB and LA inputs. If COUNT is asserted (when CLR and LOAD are not asserted), the flip-flop's contents are incremented: 00 becomes 01, 01 becomes 10, 10 becomes 11, and 11 becomes 00. When the counter is in state 11, RCO is asserted. Implement the counter using D flip-flops and as few logic components as possible. Hint: Use 4-to-1 multiplexers to implement your next-state function. You may also use XOR gates, as well as standard AND, OR, and NOT gates.