Part 1:
With the assistance of the academic supervisor, complete the process of simulating, implementing and configuring the pelican crossing controller onto the target hardware.
The main steps involved are listed below:
1. Initial Behavioural Simulation - (select the ‘test_pelican' module and invoke the ‘Simulate Behavioural Model' process). The built-in simulator ‘ISim' will be automatically started in a separate window.
2. Synthesis - this will convert the Verilog structural/behavioural descriptions into a physical circuit comprising blocks and digital components (flip-flops, gates etc.). The results can be viewed by invoking the ‘View RTL Schematic' process.
3. Implement Design (includes Synthesis plus Translation, Fitting and Generate Programming File (jedec file - ‘pelican.jed')
4. View the Fitter report summary to see how much of the CPLD device is used up by the design.
5. Check that the X-Board has it's jumpers and switches set correctly
6. Connect the Xilinx USB programming cable from the PC to the CPLD project.
7. Configure the device using the ‘Configure Device (iMPACT)' process. This process involves the software identifying and cable and establishing the boundary-scan connection to the CPLD on the board. The programming file ‘pelican.jed' is then associated with the device
prior to programming.
8. Test the design in hardware, verify and make notes regarding practical operation.
Read the information provided below for the second lab session. Prepare for the second session by creating some initial designs and performing simulations.
Part 2:
Modify the Pedestrian Crossing design implemented in session 1 to include the following additional features:
- Add a single 7-segment display to indicate the state of the ‘pelcont' finite state machine in decimal. Use one of the two 7-segment displays on the plug-in display module shown in the image below:
- The existing design responds to the pressing of the ‘Pedestrian' button (PED) such that the lights change from green to amber immediately. Modify the design so that the lights will only change if a vehicle has not been detected (by the detector buried in the road) for 5 seconds. Simulate the operation of the vehicle detector by means of a switch (see plug-in sliding switch module below), a logic-1 indicates the presence of a vehicle.
Final report - what to hand in
The report should be formally presented (bound with front and rear covers, title, date, course etc.)
Include a minimum of the following:
- Print outs of all Verilog-HDL sources (designs and test-fixtures for your modified version, created for session 2), highlighting changes made
when compared to original versions.
- Sources should be presented neatly and correctly indented, include appropriate comments and headers.
- Draw a state diagram for the ‘pelcont.v' state machine module after the modifications have been implemented. Fully explain the operation of modified machine.
- Include a modified block diagram clearly illustrating the structure of the new design (session 2).
- Print outs of all simulation waveforms (initial and modified design). Include comments/annotations to help explain results. Include a brief
written explanation of the operation of your modified design.
- Summary of CPLD Fitting report (device usage statistics for initial and modified design).
- Brief notes on the use of the CPLD board and download cable, explain how the designs were verified in hardware.