1. Make necessary changes in the UART receiver VHDL code so that it uses a 16X bit clock instead of an 8X bit clock. Using a faster sampling clock can improve the noise immunity of the receiver.
2. (a) Write a VHDL test bench for the UART. Include cases to test overrun error, framing error, noise causing a false start, change of BAUD rate, and so on. Simulate the VHDL code.
(b) If suitable hardware is available, write a simpler test bench to allow a loop-back test with TxD externally connected to RxD. Synthesize the test bench along with the UART, download to the target device, and verify correct operation of the hardware.