How would you program the pmmus tc register to implement a, Computer Engineering

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How would you program the pmmus tc register to implement a

Question: 1. How would you program the PMMUs TC register to implement a two-level page system with a page size of 8 Kbytes and a 30-bit logical address? There is no unique answer to this question and you must state your assumptions.

2. Why can some of the PMMUs caches page descriptors be locked and kept in the ATC permanently? What are the dangers of locking these descriptors, and how does the PMMU try to protect you?

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