A) How to decide the shortest possible clock period for a synchronous circuit with the flop-based clocking? What is the hold time of a register? How does the hold time constrain the circuit delays for a synchronous circuit?
b) Consider a pipeline stage in a flop-based clocking scheme. The setup and hold times for the flops are both 2 unit of time. The contamination and propagation delays of the combinational logic are 3 and 5 units of time. The clock-to-q contamination and propagation delays of the flops are both 1 unit of time. Can you clock the pipeline with a clock period of 7 units of time? Why?
C) Consider the flop-based clocking. How to fix setup and hold violations?
List all possible solutions by considering the following aspects:
1) Increase path delays; 2) decrease path delays; 3) work on fast paths; 4) work on slow paths.