Question: Chip Architecture: As described above in Exercise, a full-adder takes an area of 256 x 2 (16 x on a side). Thus, a 32-bit adder is 8K x 2, and a 32-bit recoded multiplier is 128K x 2
• How many multiplications and additions per second can be performed on a chip in 2005 and 2010? Discuss some possible uses for chips with this level of performance.
Exercise: Arithmetic Scaling: A 32-bit integer multiplier uses a 32 x 16 array of full adders. 8 Each full adder, along with its associated multiplexer, is 16x on a side. How many chips, or what fraction of a chip, does it take to make a 32 x 32 integer multiplier in 1965, 1985, and 2005? Each full adder has a delay of one gate delay (as shown in Figure), and the worst case path through the multiplier goes through nine full adders. How many multiplications per second can be realized per chip in 1965, 1985, and 2005? At what rate does this quantity scale?
