How address and data lines are demultiplexed in 8085?
AD0-AD7 lines are multiplexed and the lower half of address A0-A7 is available only during T1 of the machine cycle. This lower half of address is also essential during T2 and T3 of the machine cycle lower half of address is also essential during T2 &T3 of machine cycle to access particular location in memory or I/O part .this means that the lower half of an address bus must be latched in T1 of the machine cycle. The latching of lower half of an address is completed by using external latch and ALE signal from 8085.