Design and implement the processor shown in Figure 1 using VHDL code as follows:
1. Create a new Quartus II project for this exercise.
2. Generate the required VHDL ?le, include it in your project, and compile the circuit. A suggested skeleton of the VHDL code is shown in parts a and b of Figure 2, and some subcircuit entities that can be used in this code appear in Figure 2c.
3. Use functional simulation to verify that your code is correct. An example of the output produced by a functional simulation for a correctly-designed circuit is given in Figure 3. It shows the value (2000)16 being loaded into IR from DIN at time 30 ns. This pattern (the leftmost bits of DIN are connected to IR) represents the instruction mvi R0,#D, where the value D = 5 is loaded into R0 on the clock edge at 50 ns. The simulation then shows the instruction mv R1,R0 at 90 ns, add R0,R1 at 110 ns, and sub R0,R0 at 190 ns.
Note that the simulation output shows DIN as a 4-digit hexadecimal number, and it shows the contents of IR as a 3-digit octal number.
4. Create a new Quartus II project which will be used for implementation of the circuit on the Altera DE2- series board. This project should consist of a top-level entity that contains the appropriate input and output ports for the Altera board. Instantiate your processor in this top-level entity. Use switches SW15 0 to drive the DIN input port of the processor and use switch SW17 to drive the Run input. Also, use push button KEY0 for Resetn and KEY1 for Clock. Connect the processor bus wires to LEDR15 0 and connect the Done signal
to LEDR17.
5. Add to your project the necessary pin assignments for the DE2-series board. Compile the circuit and down- load it into the FPGA chip.
6. Test the functionality of your design by toggling the switches and observing the LEDs. Since the processor's clock input is controlled by a push button switch, it is easy to step through the execution of instructions and observe the behavior of the circuit.
LIBRARY ieee; USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY proc IS
PORT ( DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Resetn, Clock, Run : IN STD_LOGIC;
Done : BUFFER STD_LOGIC;
BusWires : BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0));
END proc;
ARCHITECTURE Behavior OF proc IS
: : : declare components
: : : declare signals
TYPE State_type IS (T0, T1, T2, T3);
SIGNAL Tstep_Q, Tstep_D: State_type;
: : :
BEGIN
High <= '1';
I <= IR(1 TO 3);
decX: dec3to8 PORT MAP (IR(4 TO 6), High, Xreg);
decY: dec3to8 PORT MAP (IR(7 TO 9), High, Yreg);
statetable: PROCESS (Tstep_Q, Run, Done)
BEGIN
CASE Tstep_Q IS
WHEN T0 => IF(Run = '0') THEN Tstep_D <= T0;
ELSE Tstep_D <= T1;
END IF; - - data is loaded into IR in this time step
: : : other states
END CASE;
END PROCESS;
controlsignals: PROCESS (Tstep_Q, I, Xreg, Yreg)
BEGIN
: : : specify initial values
CASE Tstep_Q IS
WHEN T0 => - - store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
WHEN T1 => - - de?ne signals in time step T1
CASE I IS
: : :
END CASE;
WHEN T2 => - - de?ne signals in time step T2
CASE I IS
: : :
END CASE;
WHEN T3 => - - de?ne signals in time step T3
CASE I IS
: : :
END CASE;
END CASE;
END PROCESS;
fsm?ip?ops: PROCESS (Clock, Resetn, Tstep_D)
BEGIN
: : :
END PROCESS;
reg_0: regn PORT MAP (BusWires, Rin(0), Clock, R0);
: : : instantiate other registers and the adder/subtracter unit
: : : de?ne the bus
ND Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec3to8 IS
PORT ( W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
En : IN STD_LOGIC;
Y : OUT STD_LOGIC_VECTOR(0 TO 7));
END dec3to8;
ARCHITECTURE Behavior OF dec3to8 IS
BEGIN
PROCESS (W, En)
BEGIN
IF En = '1' THEN
CASE W IS
WHEN "000" => Y <= "10000000";
WHEN "001" => Y <= "01000000";
WHEN "010" => Y <= "00100000";
WHEN "011" => Y <= "00010000";
WHEN "100" => Y <= "00001000";
WHEN "101" => Y <= "00000100";
WHEN "110" => Y <= "00000010";
WHEN "111" => Y <= "00000001";
END CASE;
ELSE
Y <= "00000000";
END IF;
END PROCESS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY regn IS
GENERIC (n : INTEGER := 16);
PORT ( R : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
Rin, Clock : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0));
END regn;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS (Clock)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF Rin = '1' THEN
Q <= R;
END IF;
END IF;
END PROCESS;
END Behavior;
Attachment:- Sample-Project-Proposal-01.pdf