Design a 4-bit right-shift register using an FPGA with logic blocks as in Figure 6-1(a). When the register is clocked, the register loads if Ld = 1 and En = 1, it shifts right when Ld = 0 and En = 1, and nothing happens when En = 0. Si and So are the shift input and output of the register. D30 and Q30 are the parallel inputs and outputs, respectively. The next-state equation for the leftmost flip-flop is Q3+ = En'Q3 + En (Ld D3 + Ld' Si).
(a) Give the next-state equations for the other three flip-flops.
(b) Determine the minimum number of Figure 6-1(a) logic blocks required to implement the shift register.
(c) For the left block, give the input connections and the internal paths on a copy of Figure 6-1(a). Also, give the X and Y functions.
