4. Gate sizing: Find the best logical implementation (with respect to delay) of an 8-input AND gate which drives a fanout of 100, and an 8-input AND gate which drives a fanout of 10,000. While a good rule of thumb for a fast design is a fanout of 4, we will see in this problem that, for real circuits, the question of fastest fanout is a little more complex. As we change the number of stages, and the logic needed per stage, we are changing both the parasitic delay and the effort delay. The best topology minimizes the total delay and depends on the relationship between parasitic delay changes and fanout. For the fanout of 100 case, you will need to consider a few options to solve the
problem.