Assignment
Problem 1
Consider the pipelined implementation (without forwarding and/or stalling) of the MIPS microprocessor as given below.
(a) Explain how an I-type load instruction would execute in this pipelined implementation. Show clearly that the result is written back in the proper Destination Register.
(b) Define data dependency hazards and explain why they may occur in this implementation.
(c) Show that a memory write (store) instruction cannot cause a data dependency hazard.
(d) Can a store instruction be part of a data dependency hazard? Explain your answer.
(e) Considering R, I and J-type instructions, explain how to detect data dependency hazards for all possible instruction-type sequences.
Problem 2
Consider the design of a stalling control for a pipelined implementation of the MIPS data path (Figure given in Problem 1).
(a) Design the Hazard Detection Unit that triggers the Stall Control Mechanism by activating a flag (hazard detected).
(b) Define the control lines that need to be used / added to the figure in Problem 1 to enable the stalling mechanism. Explain how your solution stalls the pipe for the exact number of clock cycles needed. Does your solution work when more than one hazard is found in the pipeline?
Problem 3
Consider 512Kx8bits dynamic RAM chips where the memory access time is 2/3 of the memory cycle time. These chips have an Address Bus, a bi-directional Data Bus, a Read/Write control line and a Chip Select line.
(a) Draw the diagram of a memory organization that will contain 4 megabytes, will have a 32-bit bi-directional data bus and will yield one word (32-bits) every access time if words are read from consecutive memory locations (in bursts). Clearly show and explain the number of memory chips used, how your design is capable of reading one word every memory read access time, and which bits in the address are used to select a word from your memory organization.
(b) For this memory organization, can one write a block of consecutive words faster than one every memory cycle time?
(c) Suggest a timing such that words are read faster than one every access time (assume that data appears on the memory chips' data bus instantaneously at the time it becomes available).
Problem 4
Consider a RISC microprocessor, like the MIPS presented in the textbook, for which we want to implement the full addressable space using byte addressability and 32-bit addresses. Assume we have a 320GB hard disk, a 1GB main memory, a 2MB L2 Cache and a 512KB internal Cache.
Assume that we define a memory hierarchy based on a block size of 32KB (block = page).
(a) How many blocks can be stored in each level of the memory hierarchy?
(b) Consider the three cache organizations (Direct, Fully Associative, and Set Associative Mapping). Explain how each of them works as well as the advantages and disadvantages for each organization.
Attachment:- MIPS.rar