Compare the 2's complement and sign-magnitude adders designed above. Estimate the area in terms of number of 1-bit full-adders and additional 2-input logic gates. For performance, use the timing analysis tool provided in the Xilinx Tools as follows: In the Process Window, go to Implement Design ? Map Report ? Timing. Double click on Timing to perform timing analysis on your circuit. A ( v ) near that indicates successful completion of the analysis. Now double click on Timing Report in the submenu to pull
up the Timing Report. This report is a textual version of your circuits timing characteristics. It gives the timing paths from (all) inputs to (all) outputs if a path exists between them. Take time to analyze the report generated in the context of the design you completed and determine the worst case delay through your circuit.