Elucidate the purpose of GDTR. If the microprocessor sends linear address 00200000H to paging mechanism, which paging directory entry and which page table entry is accessed?
GDTR (global descriptor table register) and IDTR (interrupt descriptor table register) comprise the base addresses of descriptor table and its limit. Limit of each descriptor table is 16 bits as maximum table length is 64 Kbytes. When the protected mode operation is desired, address of the global descriptor table and its limit are loaded into the GDTR.
For linear address 00000000H - 003FFFFFH, first entry of the page directory is accessed. Every page directory entry signifies or repages a 4-Mbyte section of the memory system. Contents of the page directory select a page table which is indexed by the next 10 bits of the linear address. This means that address 00000000H - 00000FFFH selects page directory entry 0 and page table entry 0.